1. Field of the Disclosure
The present disclosure generally relates to the formation of semiconductor devices, and, more specifically, to various methods of forming nanowire devices with doped extension regions and the resulting devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs (central processing units), storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide semiconductor field effect transistors (MOSFETs or FETs) represent one important element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate structure positioned above the channel region. These elements are sometimes referred to as the source, drain, channel, and gate, respectively. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and prevent the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed, and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g. silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device.
Another form of 3D semiconductor device employs so-called nanowire structures for the channel region of the device. There are several known techniques for forming such nanowire structures. As the name implies, at the completion of the fabrication process, the nanowire structures typically have a generally circular cross-sectional configuration. Nanowire devices are considered to be one option for solving the constant and continuous demand for semiconductor devices with smaller feature sizes. However, the manufacture of nanowire devices is a very complex process.
FIG. 1 is a simplified view of an illustrative nanowire device 100 at an early stage of manufacturing that is formed on a semiconducting substrate 10. FIG. 1 is provided so as to explain one example of how nanowire devices may be fabricated. At the point of fabrication depicted in FIG. 1, various layers of semiconducting material 11, 12, 13 and 14 were formed above the substrate 10. In general, in the depicted example, the layers 11 and 13 include a semiconductor material that may be selectively removed or etched relative to the materials used for the semiconducting material layers 12 and 14. As described more fully below, portions of the semiconductor material layers 11 and 13 will be removed while the semiconducting material layers 12 and 14 will be left in place. Thus, the portions of the semiconducting material layers 11 and 13 within the channel region of the device are sacrificial in nature. The semiconductor materials 11, 12, 13 and 14 may include a variety of different materials such as, for example, silicon, doped silicon, silicon-carbon, silicon-germanium, a III-V material, germanium, etc., and they may be formed to any desired thickness by performing any appropriate process, e.g., an epitaxial growth process, deposition plus ion implantation, etc. In one embodiment, the semiconducting material layers 11 and 13 may be made from silicon-germanium, while the semiconducting material layers 12 and 14 may be made from silicon.
The gate structure 25 may include a variety of different materials and a variety of configurations. As shown, the gate structure 25 includes a gate insulation layer 25A, a gate electrode 25B, and a gate cap layer 25C. A deposition or thermal growth process may be performed to form the gate insulation layer 25A, which may be made of silicon dioxide in one embodiment. Thereafter, the materials for the gate electrode 25B and the gate cap layer 25C may be deposited above the device 100, and the layers may be patterned by performing photolithographic and etching techniques. The gate electrode 25B may include a variety of materials, such as polysilicon or amorphous silicon.
When the device 100 is completed, there will be two illustrative nanowires in the nanowire channel structure that will be arranged in the form of a vertical stack, where one nanowire is positioned above the other nanowire. To reduce parasitic resistance, the regions between the spacers may be doped. Each of the nanowires may be equally doped to reduce device performance variability. However, each nanowire will not have the same characteristics when formed by performing known techniques. Specifically, performing known doping techniques results in the nanowires having different “dopant profiles.” A dopant profile of a nanowire is defined by the location, concentration and type of dopant within the nanowire. Thus, two nanowires with the same dopant profiles are doped with substantially the same types of dopants, in substantially the same concentration, and at substantially the same locations within the nanowires. Ideally, all of the nanowires in a device should have substantially the same dopant profile. Nanowires with different dopant profiles result in devices with uneven performance, reliability and unpredictable costs for testing.
To reduce production cost and increase circuit functionality, the semiconductor industry strives to increase the number of transistors and their speed or performance within an integrated circuit. The present disclosure is directed to various methods of forming nanowire devices with doped extension regions and the resulting devices to realize such gains. Additionally, the methods and devices disclosed herein reduce or eliminate one or more of the problems identified above.